A semiconductor device is formed by patterning one or more layers on a semiconductor substrate or wafer. In the semiconductor manufacturing process, the overlay between previous patterned layers and a current layer to be patterned is controlled to within a tight tolerance, referred to as an overlay error budget. Typically, overlay between different layers has been measured by optical microscopy of relatively large targets specifically designed for overlay analysis. These targets are referred to as optical overlay targets, examples of which are shown in FIGS. 1A-1D. The sizes of these overlay targets vary from between 10 μm and 40 μm.
Overlay is independently measured for each subsequently patterned layer with respect to the previously patterned layer, thus requiring overlay targets positioned on each layer. Moreover, to allow for independent measurement, overlay targets should not overlap. Overlay targets thus require a significant amount of substrate area because of these size and non-overlap requirements. To improve overlay measurement precision, additional sampling is desired. Thus, there exists necessarily a trade-off between overlay target size and location with overlay measurement precision due to semiconductor device area considerations.
To accommodate these requirements, the targets are typically provided in a dicing area, which is used to separate the semiconductor devices into individual chips. For example, a section 200 of a wafer is shown in FIG. 2. A semiconductor chip 202 includes one or more circuit blocks 204 formed by patterning of successive layers on the wafer. Optical overlay targets 206 are provided in dicing lanes 208 to provide alignment control between the patterning of the different layers. After formation of the semiconductor chip 202 is complete, the dicing lanes 208 are cut with a dicing saw to create individual chips.
However, there can be a significant difference in the overlay at optical overlay targets and at actual device patterns due to differences in location on a semiconductor device or wafer. Accordingly, the optical overlay targets 206 located in dicing lanes 208 may not adequately reflect the overlay between pattern features in various layers of the semiconductor chip 202. Such a difference may be negligible when dealing with larger feature sizes. However, as pattern features continue to shrink, tighter tolerances are required such that any difference in overlay between the overlay targets and the actual device patterns becomes increasingly important. For example, for pattern features in the 22 nm feature size regime overlay tolerances less than 10 nm are necessary.